This invention relates to a semiconductor device as typified by a semiconductor memory device, its fabrication method and its design method. More particularly, the present invention relates to a semiconductor device suitable for a high integration density semiconductor device, its fabrication method and its design method.
In the development of a high integration density semiconductor device, efforts at reducing the size of a device isolation region for electrically isolating adjacent device formation regions has been a critical problem.
A thermal oxide film has been generally used for forming this device isolation region. To locally form the thermal oxide film, a silicon nitride film is deposited on the surface of the device formation region and then a thermal oxidation reaction is carried out.
This thermal oxidation reaction proceeds due to diffusion of an oxidation seed, that is, oxygen or steam vapor, and due to a reaction on the interface between an oxide film and a semiconductor substrate.
Because diffusion of the oxidation seed takes place three-dimensionally, such diffusion is extended also to a location below the silicon nitride film at which location the oxide film is not desired to be formed. Because the shape of growth of the oxide film below the silicon nitride film has a shape of the beak of a bird, it is generally referred to as a xe2x80x9cbird""s beakxe2x80x9d. The growth of the bird""s beak reduces an area of the device formation region. Therefore, restriction of this growth is important towards accomplishing a high integration density.
To restrict the growth of the bird""s beak, a technology which forms grooves on a semiconductor substrate near the end portion of the silicon nitride film and oxidizes the inner wall of the grooves to form the device isolation regions has been developed in the past. A concrete method is described in JP-A-3-96249 and JP-A-4-127433, for example.
The silicon nitride film used as an antioxidation film generally has a great internal stress. Therefore, a high stress occurs in the proximity of the semiconductor substrate surface, too. When a shear stress component (resolved shear stress) in a direction of a slip plane of a crystal exceeds a limit value, dislocation occurs, and electric characteristics of a device are remarkably deteriorated.
The strength of the semiconductor substrate remarkably drops near 1,000xc2x0 C. at which a thermal oxidation step is carried out in comparison with a temperature near room temperature, and dislocation is extremely likely to occur. Accordingly, stress control is also very important.
In the ordinary thermal oxidation process, a thin thermal oxide film (which will be hereinafter referred to as a xe2x80x9cpad oxide filmxe2x80x9d) is first formed on the semiconductor substrate surface so as to protect the semiconductor substrate from the internal stress of the silicon nitride film, and the silicon nitride film is then deposited. The value of the resolved shear stress occurring in the semiconductor substrate below the end portion of the silicon nitride film can be limited to be below the dislocation occurrence limit by controlling the film thickness of this pad oxide film, and the occurrence of dislocation can be thus prevented.
When the grooves are formed on the substrate surface to restrict the growth of the bird""s beak, however, the stress field occurring near the substrate surface is likely to change, and the value of the resolved shear stress increases in accordance with the depth of the grooves formed.
FIGS. 2A and 2B of the accompanying drawings illustrate an example of analysis of the relationship between the depth of the groove formed on the substrate surface and the resulting stress. The abscissa in FIG. 2B represents the groove depth (that is, an over-etch quantity D of the substrate) and the ordinate represents the maximum stress (that is, a maximum stress at the mask end).
Incidentally, the ordinate is normalized by a stress value before the formation of the groove. It can be understood that the resulting stress increases due to the formation of the groove. A stress concentration field has existed at only the end portion of the silicon nitride film before the formation of the groove, but when the groove is formed, it also takes place at the lower end portion of the groove formed, too. These two stress concentration fields interfere with each other and eventually increase the resolved shear stress component in the direction of the slip plane on the sidewalls of the groove.
In this instance, there is the case where the resulting stress exceeds the dislocation occurrence limit value with the formation of the groove even when the stress value before the formation of the groove is below the dislocation occurrence limit value. As will be later described, this stress increase has dependence on the pattern dimension. Accordingly, when the grooves are formed on the semiconductor substrate surface, an appropriate counter-measure must be taken lest the increased stress exceeds the dislocation occurrence limit value.
It is an object of the present invention to provide a device structure, or a groove formation method, which restricts the resulting stress below the dislocation occurrence limit value when the grooves are formed on the semiconductor substrate surface (particularly in the thermal oxidation process).
It is another object of the present invention to provide a semiconductor device structure, and fabrication and design methods thereof, which prevent the occurrence of crystal defects in the thermal oxidation process in a semiconductor production process.
Incidentally, the term xe2x80x9cdislocation occurrence limit stressxe2x80x9d means a limit value of the stress above which dislocation occurs in the silicon single crystal. The shear stress in the direction of the (111) slip plane of the silicon single crystal is used hereby as the stress, and is generally referred to as the xe2x80x9cresolved shear stressxe2x80x9d.
This stress value changes with a production method of a crystal, with an impurity concentration, with a temperature, and so forth. Therefore, a value corresponding to the material or temperature practically used must be employed.
To accomplish the objects described above, the present invention stipulates the structural dimension so that a ratio of the width of the device formation region to the width of the device isolation region adjacent to the device formation region keeps a predetermined value at which the resulting stress is below the dislocation occurrence limit value.
When the width dimension L, taken from 0.1 to 125 xcexcm, of the device formation region is defined, the width dimension S, taken from 0.1 to 2.5 xcexcm of the device isolation regions so encompassing the device formation region as to correspond to a predetermined groove depth (in which the groove is formed in the device isolation area before the isolation oxide film is formed), is made sufficiently great so that the ratio L/S is below a predetermined value. When the minimum value of the S dimension is defined, the width dimension L of the device formation region adjacent to the device isolation regions is designed so that the ratio L/S is below the predetermined value, by reducing the size of the device formation region or dividing the device formation region.
The structural design can be made by executing stress analysis by using a finite element method, and the L or S dimension is stipulated so that the stress analysis (predicted) value is smaller than the dislocation occurrence limit stress.
Generally, a semiconductor device such as a memory device comprises a memory portion and a peripheral circuit portion as shown in FIG. 16. In the memory portion, very small device formation regions having a size of about 1 xcexcm and having the same shape are periodically arranged with the device isolation regions being interposed between them. In this memory portion, the values of L and S are not greater than about 1 xcexcm in most cases.
In the peripheral circuit portion, on the other hand, considerably greater device formation regions are so arranged as to have the device isolation regions interposed between them. In this case, the shapes of the device formation regions adjacent to one another are not always the same. The values L and S described in the present invention are expressed by the values in the direction in which the S value of the adjacent device isolation region becomes minimal, that is, by the dimension of the major or minor side of the device formation region, and does not use the diagonal direction (e.g. L1, L2 or S1, S2, S3, S4 in FIG. 16). in the peripheral circuit, the L value exceeds several microns (xcexcm) in many cases but the S value is mostly equal to that of the memory portion. Accordingly, the stress value is generally higher in the peripheral circuit portion than in the memory portion.
The value of the resulting stress changes with the internal stress of the silicon nitride film, its thickness, the thickness of the pad oxide film, the groove formation depth and the L/S dimension. The internal stress of the silicon nitride film can be measured from the warp of the silicon substrate, and the thickness of the pad oxide film, too, can be measured.
The groove formation depth and the L/S dimensions are given as the design values. Therefore, structural analysis is possible. Analysis may be made by defining the L/S dimensions while groove formation depth is kept fixed at a predetermined value, or the depth and shape of the groove may be defined from the L/S dimensions.
The internal stress of the silicon nitride film may be measured incessantly during the fabrication process, or a value stored as the data base may be used. The thickness of the silicon nitride film may be measured incessantly, too, or a value determined from the production condition of the film may be stored as the data base and may also be used.
As to the thickness of the pad oxide film, the thickness incessantly measured may be used, or the design (predicted) value determined by the film formation condition may be used as the data base.
The dimension and the depth of the groove are defined by the etching condition. However, as will be later described, there is the case where the stress value greatly changes due to the change of the groove shape in the order of nanometer. Therefore, the value incessantly measured is preferably used, but the value predicted from the etching condition may be converted to the data base and may be used.
Structural analysis may be carried out at the design stage before production, or the dimensions at a next production stage may be determined whenever the measurement values are obtained in the production process. The stress value obtained as a result of analysis is compared with the strength data of the semiconductor substrate, and the L, S design values or the groove shape is adjusted so that the resulting (predicted) stress value does not exceed the strength.
The strength data to be compared with the analytical value may be the data of the experimental data base or the empirical values obtained by comparative examination of the past defective data (occurrence of dislocation) may be used, as well.
When the oxidation process conditions such as the thickness and internal stress of the silicon nitride film, the thickness of the pad oxide film, the groove shape, etc., are fixed, it becomes possible to analyze in advance the resulting stress in accordance with the L and S dimensions. In this case, since the L and S dimensions at which dislocation is expected to occur can be clarified, a design chart representing the dislocation occurrence region is prepared beforehand, and the L and S dimensions can be selected and determined in such a manner as to avoid the danger region, on this chart, at the design stage.
Hereinafter, the outstanding features of the present invention will be explained in accordance with categories.
(Semiconductor Memory Device)
The semiconductor memory device according to the present invention includes a memory portion and a peripheral portion formed on a semiconductor substrate, wherein each of the portions comprises device isolation regions and device formation regions made of a thermal oxide film as a principal constituent material, and wherein a ratio L/S of the width dimension S of the device isolation region and the width dimension L adjacent to one another in the peripheral circuit portion is not greater than an upper limit value which is stipulated by a dislocation occurrence limit stress value inside the semiconductor memory portion, and S is at least 0.1 xcexcm. When S becomes great, the upper limit value drops. The lower limit of S is set to at least 0.1 xcexcm in consideration of the minimum machining dimensional limit of 1-giga DRAMs (hereinafter the same). If the lower limit of S is set to 0, the device isolation region does not exist. Here, the term xe2x80x9cperipheral circuit portionxe2x80x9d represents the circuit portion which does not store the data in the memory device (hereinafter the same). This peripheral circuit portion must be arranged in such a manner as to satisfy both of the requirements that L is, preferably, as great as possible so as to increase a current capacity while the overall chip size is, preferably, as small as possible.
The value of the ratio L/S of the width dimension L of the device formation region to the width dimension S of the device isolation region adjacent thereto in the peripheral circuit portion described above, is not greater than 50, and S is at least 0.1xcexc. As to the value 50, refer to FIG. 4.
In the peripheral circuit portion, the ratio L/S of the width dimension L of the device formation region to the width dimension S of the device isolation region adjacent thereto is at least 2. it is desired from the beginning that the memory is fabricated by the minimum possible machining dimension. Accordingly, if S can be machined by 1 xcexcm, for example, it has not been necessary in the past to intentionally set L to 2 xcexcm. tn contrast, the present invention proposes that the value L/S is at least 2 so as to prevent the occurrence of dislocation even by making S small.
The width dimension of the device isolation regions encompassing the device formation regions in the peripheral circuit portion and made of the thermal oxide film as the peripheral constituent material is not smaller than the lower limit value which is defined by the relationship between the width dimension of the device formation region and the dislocation occurrence limit stress value inside the semiconductor memory device.
The width dimension of the device isolation regions encompassing the device formation region in the peripheral circuit portion and made of the thermal oxide film as the principal constituent material is, preferably, at least 0.1 xcexcm.
The width dimension of the device formation region, which is encompassed by the device isolation regions made of the thermal oxide film as the principal constituent material in the periphery circuit portion, is not greater than the upper limit value defined by the relation between the width dimension of the adjacent device isolation region and the dislocation occurrence limit stress value inside the semiconductor memory device.
The width dimension of the device formation region encompassed by the device isolation regions encompassing the device formation region in the peripheral circuit portion and made of the thermal oxide film as the principal constituent material is, preferably, up to 5 xcexcm.
Here, many device isolation regions adjacent to the device formation region L exist around, but the smaller S should be selected. The S width existing on the diagonal line of the device formation region does not merit consideration. For, the width is determined by the shortest dimension encompassing the device formation region.
Incidentally, the silicon nitride film is the one that is formed on the device formation region before thermal oxidation so as to prevent oxidation, and is removed at subsequent steps.
(Stress Analysis Method of Semiconductor Device)
The stress analysis method according to the present invention analyzes the stress occurring in the proximity of the groove formation region from the internal stress of the silicon nitride film and its thickness, the thickness of the pad oxide film, the depth of the groove to be formed in the device isolation region, the width of the device isolation region and the width of the device formation region adjacent to the device isolation region, by numerical analysis means. Here, the numerical analysis means is preferably a finite element method (hereinafter the same).
FIG. 17 shows the outline of the flow of oxidation stress analysis.
A pad oxide film is formed (71) on an initial stage substrate (wafer) by a thermal oxidation method, and a silicon nitride film is formed (72) on the pad oxide film by a CVD method. At this time, an internal stress ("sgr"i) of the silicon nitride film is taken into consideration in stress analysis. Next, stress fluctuation when pattern is effected in accordance with the dimensions S, L of the device isolation region and the device formation region is analyzed. In this case, analysis is effected while an over-etch depth D of the substrate occurring at the time of etching is taken into consideration. This state is the initial shape of the oxidation. Thermal stress analysis is made when the overall temperature is raised (74) to the oxidation temperature, and oxidation thermal analysis is thereafter effected.
The structural equation based on a viscoelastic model and used for stress analysis is shown by equation (1), where a is a stress, xcex5,xcex5xcex8 and xcex5V are a strain, a thermal strain and viscous strain, respectively, D is a material moduli matrix, xcex2 is a ratio of Young""s moduli E1 and E2 in the viscoelastic model, and "sgr"i is an intrinsic stress of a thin film, and the detail of the stress analysis using this structural equation is described in the cited reference:
xe2x80x83xcex94s=(D+xcex94D)(xcex94xcex5xe2x88x92xcex94xcex5qxe2x88x92bxcex94xcex5v)+xcex94Dxc2x7D-1("sgr"xe2x88x92"sgr"i)xe2x80x83xe2x80x83(1)
"sgr": stress
xcex5: strain
xcex5xcex8: thermal strain
xcex5v: viscous strain
D: material moduli matrix
xcex2: ratio of Young""s moduli E1 and E2
"sgr"i : intrinsic stress.
(Stress Distribution Chart of Semiconductor Device)
A stress distribution chart effective for the present invention represents the stress, which occurs in the proximity of the groove formation region and is determined by using a numerical analysis means from the internal stress of the silicon nitride film, its thickness, the thickness of the pad oxide film, the depth of the groove formed in the device isolation region, the width of the device isolation region and the width of the device formation region adjacent to the device isolation region, by using the device isolation region and the device formation region as parameters.
The stress distribution chart directly plots the stress values of the results of analysis using L and S as the parameters for each process specification as shown in FIGS. 19A to 19C, wherein the abscissa and the ordinate represent L and S. The values of the stress may be written to the chart as numerical data, or the chart may employ the contour line expression. The contour line display may be line data or a region exceeding a predetermined value may be displayed by a color or a pattern as shown in the drawing.
A design chart is prepared by dividing the stress value "sgr" by the dislocation occurrence limit stress value "sgr"c and displaying the regions, in which the quotient exceeds 1, as shown in FIGS. 20A and 20B. Since the occurrence of dislocation is predicted in the display region, a designer using this chart makes dimensional design so that the design dimensions of L and S (their combination) do not fall within this region, or when it is desired to use the dimensions falling within this region, the designer changes the process specification so that the dimension does not fall within the dislocation occurrence prediction region. As shown in the drawings, the display method of the design chart may employ individual display for each process specification, or may collectively display a plurality of process specifications.
Here, the calculation formula of "sgr"/"sgr"c can be expressed by the following equation (2), for example:
"sgr"/"sgr"c=
X
Xxe2x80x83xe2x80x83(2)
where
tp: thickness of pad oxide film (nm)
tn: thickness of nitride film (nm)
d: over etch depth of silicon substance (nm)
The stress A, which occurs in the proximity of the groove formation region and is determined by the numerical analysis means from the internal stress of the silicon nitride film, its thickness, the thickness of the pad oxide film, the depth of the groove formed in the device isolation region, the width of the device isolation region and the width of the device formation region, is normalized (A/B) by the dislocation occurrence limit stress B of the semiconductor substrate at the highest temperature of the oxidation step, and the region in which the normalization value exceeds 1 and the occurrence of dislocation is predicted is clearly represented by the design chart using the width dimensions of the device isolation region and the device formation region as the parameters. In this case, the move-back (etch-back) distance of the pad oxide film is preferably used as a parameter for representing the dislocation occurrence prediction region. The finite element method is effective for the numerical analysis means.
(Semiconductor Production Apparatus)
The first semiconductor production apparatus according to the present invention comprises means for measuring the thickness of the pad oxide film, the thickness of the silicon nitride film and its internal stress, respectively, an arithmetic unit for effecting numerical analysis by using the measurement values, and the design values of the width of the device formation region and the width of the device isolation region adjacent to the device formation region, a display device or a data display matter such as paper for displaying the design chart described above, and decides the substrate groove formation depth at the time of removal of the silicon nitride film before selective oxidation. Here, the form may be an apparatus of one package, or may be the form of a discrete system having each function.
The second semiconductor production apparatus according to the present invention comprises means for measuring the thickness of the pad oxide film, the thickness of the silicon nitride film and its internal stress, respectively, means for measuring the width of the device formation region and the width of the device isolation region adjacent to the device formation region, means for measuring the depth of the groove formed in the substrate surface at the time of removal of the silicon nitride film before selective oxidation, an arithmetic unit for effecting stress analysis by using the measurement results, a memory device for preserving design strength data (design chart or stress distribution chart), and means for deciding and displaying the move-back (etch-back) distance of the pad oxide film at which dislocation does not occur at the time of selective oxidation, by comparing the results of analysis with the strength data (see dimension B in FIG. 2A).
(Design Method of Semiconductor Device)
In the semiconductor device according to the present invention, the design method of the semiconductor device comprises a step of effecting stress analysis by using the thickness of the pad oxide film, the thickness of the silicon nitride film and its internal stress, and the substrate groove formation depth at the time of removal of the silicon nitride film before oxidation, and a step of deciding (A) the width of the device formation region and the width of the device isolation region adjacent to the device formation region, and/or (B) the groove formation depth.
(Fabrication Method of Semiconductor Device)
(A) The fabrication method of the present invention includes a step of effecting stress analysis by using the thickness of the pad oxide film, the thickness of the silicon nitride film and its internal stress, the width dimension of the device formation region, the width dimension of the device isolation region adjacent to the device formation region, and the depth of the groove formed on the substrate surface at the time of removal of the silicon nitride film before selective oxidation, and a step of deciding the move-back (etch-back) distance of the pad oxide film at which dislocation does not occur at the time of selective oxidation and etching back the pad oxide film.
(B) The pad oxide film is etched back by at least 4 nm before the thermal oxidation step.
(C) Stress (numerical) analysis is effected by using the thickness of the pad oxide film, the thickness of the silicon nitride film and its internal stress, the width of the device formation region and the width of the device isolation region adjacent to the device formation region, and the substrate groove formation depth at the time of removal of the silicon nitride film before selective oxidation can be thus determined.
(D) The width dimension of the device isolation region or the width dimension of the device formation region is determined so that the stress, which occurs in the proximity of the groove formation region and is determined by the numerical analysis means by using the internal stress of the silicon nitride film and its thickness, the thickness of the pad oxide film, the depth of the groove formed in the device isolation region, the width of the device isolation region and the width of the device formation region adjacent to the device isolation region, is not higher than the dislocation occurrence limit strength.
(E) The width dimension of the device isolation region encompassing the device formation region and made of the thermal oxide film as the principal constituent material is set to be not lower than the lower limit value which is defined by the thickness of the silicon nitride film and its internal stress, the thickness of the pad oxide film, the depth of the groove formed on the substrate surface, and the relation between the width of the device formation region and the dislocation occurrence limit stress value inside the semiconductor device.
(F) The width dimension of the device formation region encompassed by the device isolation region made of the thermal oxide film as the principal constituent material is set to be not higher than the upper limit value which is defined by the thickness of the silicon nitride film and its internal stress, the thickness of the pad oxide film, the depth of the groove formed on the substrate surface, and the relation between the width dimension of the adjacent device isolation region and the dislocation occurrence limit stress value.
(Semiconductor Device)
In the semiconductor device according to the present invention, the device formation region preferably has a width dimension of at least 4 xcexcm and the width dimension of the device isolation region encompassing the device formation region and made of the thermal oxide film as the principal constituent material is preferably at least 1 xcexcm.
The smaller the S dimension and the greater the L dimension, the more likely becomes the resulting stress to increase. In the example shown in FIG. 3B, for example, when the S dimension is 2 xcexcm, the resulting stress exceeds the dislocation occurrence limit stress in the region in which the L dimension is at least 2 xcexcm. When the S dimension is 4 xcexcm, on the other hand, it is when the L dimension is at least 4 xcexcm that the resulting stress exceeds the dislocation occurrence limit.
Accordingly, when the dimensions and the arrangement of the device isolation region and the device formation region are designed, either one of the L and S dimensions can be determined first, and then the other is designed to the dimensional region in which dislocation does not occur.
From this aspect, each of the inventions described above sets the ratio of the width dimension of the device formation region to that of the device isolation region adjacent to the former to the value at which the resulting stress is below the dislocation occurrence limit value.